The demands of both communication technology and computer technology has led to greater requirements in the field of III-V integrated circuit technology. These requirements include greater speed, more sensitivity, higher gain, greater packing density and closer tolerances for circuit elements.
Particularly important in the fabrication of III-V integrated circuits is the nature of the substrate material. Particularly significant is the resistivity of the substrate so as to effect isolation of various elements of the integrated circuit and the trap density at the interface between substrate and circuit. High trap density can lead to hysteresis affects in the current vs voltage characteristics of the integrated circuits which effects certain desirable characteristics of the circuit such as noise performance and circuit stability.
Conventional integrated circuits using field-effect transistor (FET) elements or junction field effect transistor (JFET) elements generally use semi-insulating indium phosphide substrates to obtain electrical isolation between circuit components. Such circuits are discussed in a number of references including D. Wake et al, IEEE Electron Device Letters, Vol. EDL-5, No. 7 (July 1984) and Y. G. Chai et al, IEEE Electron Device Letters, Vol. EDL-4, No. 7 (July 1983). Although these circuits employing semi-insulating indium phosphide substrates work, circuits with substantially lower defect density between substrate and circuit elements are highly desirable. Also, in III-V semiconductor circuits employing multiple FET elements or FET elements incorporated with other device elements such as photodetector elements or diode elements, semi-insulating substrates often limit flexibility, ease of integration or advantageous integration geometries.